An insufficient DRAM address validation in PMFW may allow a privileged attacker to perform a DMA read from an invalid DRAM address to SRAM, potentially resulting in loss of data integrity.
Fixes

Solution

No solution given by the vendor.


Workaround

No workaround given by the vendor.

History

Mon, 04 Nov 2024 18:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-125

Wed, 14 Aug 2024 15:30:00 +0000

Type Values Removed Values Added
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


Tue, 13 Aug 2024 17:00:00 +0000

Type Values Removed Values Added
Description An insufficient DRAM address validation in PMFW may allow a privileged attacker to perform a DMA read from an invalid DRAM address to SRAM, potentially resulting in loss of data integrity.
References
Metrics cvssV3_1

{'score': 5.2, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:U/C:L/I:H/A:L'}


cve-icon MITRE

Status: PUBLISHED

Assigner: AMD

Published:

Updated: 2024-11-04T17:20:36.376Z

Reserved: 2022-10-27T18:53:39.735Z

Link: CVE-2023-20509

cve-icon Vulnrichment

Updated: 2024-08-14T14:31:00.815Z

cve-icon NVD

Status : Awaiting Analysis

Published: 2024-08-13T17:15:18.590

Modified: 2024-11-04T18:35:02.490

Link: CVE-2023-20509

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.