An insufficient DRAM address validation in PMFW may allow a privileged attacker to perform a DMA read from an invalid DRAM address to SRAM, potentially resulting in loss of data integrity.
Metrics
Affected Vendors & Products
References
History
Mon, 04 Nov 2024 18:15:00 +0000
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Weaknesses | CWE-125 |
Wed, 14 Aug 2024 15:30:00 +0000
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Metrics |
ssvc
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Tue, 13 Aug 2024 17:00:00 +0000
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Description | An insufficient DRAM address validation in PMFW may allow a privileged attacker to perform a DMA read from an invalid DRAM address to SRAM, potentially resulting in loss of data integrity. | |
References |
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Metrics |
cvssV3_1
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MITRE
Status: PUBLISHED
Assigner: AMD
Published: 2024-08-13T16:52:00.677Z
Updated: 2024-11-04T17:20:36.376Z
Reserved: 2022-10-27T18:53:39.735Z
Link: CVE-2023-20509
Vulnrichment
Updated: 2024-08-14T14:31:00.815Z
NVD
Status : Awaiting Analysis
Published: 2024-08-13T17:15:18.590
Modified: 2024-11-04T18:35:02.490
Link: CVE-2023-20509
Redhat
No data.