The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.

Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
Advisories
Source ID Title
EUVD EUVD EUVD-2023-38407 The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
Fixes

Solution

No solution given by the vendor.


Workaround

Not passing through physical devices to guests will avoid the vulnerability.

History

Wed, 18 Jun 2025 16:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-672
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'total'}, 'version': '2.0.3'}


cve-icon MITRE

Status: PUBLISHED

Assigner: XEN

Published:

Updated: 2025-06-18T15:48:27.234Z

Reserved: 2023-06-01T10:44:17.065Z

Link: CVE-2023-34326

cve-icon Vulnrichment

Updated: 2024-08-02T16:10:06.955Z

cve-icon NVD

Status : Modified

Published: 2024-01-05T17:15:08.637

Modified: 2025-06-18T16:15:21.167

Link: CVE-2023-34326

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.