The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Metrics
Affected Vendors & Products
Advisories
No advisories yet.
Fixes
Solution
No solution given by the vendor.
Workaround
No workaround given by the vendor.
References
History
Sun, 23 Nov 2025 17:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state. | |
| Weaknesses | CWE-1284 | |
| References |
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| Metrics |
cvssV4_0
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Status: PUBLISHED
Assigner: AMD
Published:
Updated: 2025-11-23T17:15:28.948Z
Reserved: 2025-07-23T15:01:52.882Z
Link: CVE-2025-54515
No data.
Status : Received
Published: 2025-11-23T18:15:55.163
Modified: 2025-11-23T18:15:55.163
Link: CVE-2025-54515
No data.
OpenCVE Enrichment
No data.