The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Advisories

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Fixes

Solution

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Workaround

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History

Sun, 23 Nov 2025 17:30:00 +0000

Type Values Removed Values Added
Description The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Weaknesses CWE-1284
References
Metrics cvssV4_0

{'score': 1, 'vector': 'CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N'}


cve-icon MITRE

Status: PUBLISHED

Assigner: AMD

Published:

Updated: 2025-11-23T17:15:28.948Z

Reserved: 2025-07-23T15:01:52.882Z

Link: CVE-2025-54515

cve-icon Vulnrichment

No data.

cve-icon NVD

Status : Received

Published: 2025-11-23T18:15:55.163

Modified: 2025-11-23T18:15:55.163

Link: CVE-2025-54515

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.