{"dataType": "CVE_RECORD", "cveMetadata": {"state": "PUBLISHED", "cveId": "CVE-2025-63384", "assignerOrgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "assignerShortName": "mitre", "dateUpdated": "2025-11-10T20:07:29.692Z", "dateReserved": "2025-10-27T00:00:00.000Z", "datePublished": "2025-11-10T00:00:00.000Z"}, "containers": {"cna": {"providerMetadata": {"orgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "shortName": "mitre", "dateUpdated": "2025-11-10T20:07:29.692Z"}, "descriptions": [{"lang": "en", "value": "A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability."}], "affected": [{"vendor": "n/a", "product": "n/a", "versions": [{"version": "n/a", "status": "affected"}]}], "references": [{"url": "https://github.com/chipsalliance/rocket-chip.git"}, {"url": "https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET"}], "problemTypes": [{"descriptions": [{"type": "text", "lang": "en", "description": "n/a"}]}]}}, "dataVersion": "5.2"}

{}

{"cveTags": [], "descriptions": [{"lang": "en", "value": "A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability."}], "id": "CVE-2025-63384", "lastModified": "2025-11-10T20:15:49.013", "metrics": {}, "published": "2025-11-10T20:15:49.013", "references": [{"source": "cve@mitre.org", "url": "https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET"}, {"source": "cve@mitre.org", "url": "https://github.com/chipsalliance/rocket-chip.git"}], "sourceIdentifier": "cve@mitre.org", "vulnStatus": "Received"}

{}

{}