Description
The ARM64 MMU back-end allocated address space identifiers (ASIDs) for memory domains with a bare round-robin counter in arch_mem_domain_init() (arch/arm64/core/mmu.c). VM_ASID_BITS is 8, so only 255 ASIDs exist; once the counter wrapped, arch_mem_domain_init() could hand an ASID to a new domain while a still-live domain held the same one. Domain-private mappings are installed non-global (MT_NG), so the ASID is the only tag separating one domain's cached translations from another's in the TLB.

The context-switch path in z_arm64_swap_ptables() only flushes the TLB when the outgoing and incoming domains carry the same ASID, which does not cover a duplicate reached through a third domain: for domains A and C sharing an ASID and an unrelated domain B, the schedule A -> B -> C never takes the flush branch, so the ASID-tagged entries A populated remain resident while C runs. Under SMP two live domains sharing an ASID can additionally be resident on two CPUs at once, which the architecture does not allow for distinct translation-table sets.

Triggering the wrap requires a CONFIG_USERSPACE application on ARM64 that creates more than 255 memory domains over its lifetime; k_mem_domain_init() and k_mem_domain_deinit() are supervisor-only APIs and are not exposed as syscalls, so an unprivileged thread cannot drive the counter directly. Once two live domains alias, however, a user-mode thread in one domain can read and write memory belonging to the other domain's partitions and thread stacks with that domain's permissions, defeating the memory-domain isolation boundary.

The fix scans the live domain_list before assigning an ASID, advances the round-robin counter past ASIDs already in use, and returns -ENOMEM when all are taken, so domain creation fails closed instead of silently aliasing.
Published: 2026-10-09
Score: 7 High
EPSS: < 1% Very Low
KEV: No
Impact: Memory Isolation Violation
Action: Immediate Patch
AI Analysis

Impact

Zephyr’s ARM64 MMU backend assigns address space identifiers (ASIDs) to memory domains using a simple round‑robin counter. With only 255 unique 8‑bit ASIDs, the counter can wrap and the code may hand an ASID that is already in use by a live domain. Because domain‑specific translations are installed as non‑global TLB entries, the ASID is the sole tag that isolates one domain’s cached TLB entries from another’s. The context‑switch routine does not flush the TLB when two different domains inadvertently share the same ASID unless the incoming and outgoing domains are identical, which allows duplicate entries to remain resident. Consequently, when two live domains alias the same ASID, a user‑mode thread in one domain can access memory belonging to the other domain, breaking the intended isolation boundary and enabling a privilege escalation within the same application.

Affected Systems

Zephyr RTOS running on ARM64 architecture. The vulnerability exists in any Zephyr build that uses the described ASID allocation scheme in arch/arm64/core/mmu.c before the commit that introduces the mitigation. No specific release identifiers are listed; therefore, all current and previous versions without the patch are affected.

Risk and Exploitability

The CVSS score of 7 signals a high‑severity bug. Exploitation requires creating more than 255 memory domains, an action only possible through supervisor‑level API calls (k_mem_domain_init/k_mem_domain_deinit). Thus the attack must originate from local kernel code or an application with kernel privileges. Once the counter wraps and an alias is created, a user‑mode thread can read or write memory allocated to other domains, effectively elevating privileges within the same user context. The EPSS score is unavailable, and the vulnerability is not listed in CISA KEV. The risk is therefore confined to systems that enable unrestricted domain creation; however, because the alias allows cross‑domain memory access, the impact is significant for those deployments.

Generated by OpenCVE AI on October 9, 2026 at 08:51 UTC.

Remediation

No solution or workaround provided in the CVE record.

OpenCVE Recommended Actions

  • Upgrade the Zephyr firmware to a release that includes the commit that scans the live domain list before assigning an ASID and returns an error when all ASIDs are occupied.
  • If an upgrade is not possible, restrict the maximum number of memory domains that any application can create to fewer than 255, thereby preventing the ASID counter from wrapping while hot‑plugging domains.
  • As an interim measure, disable or retire unused memory domains and audit user‑space applications to ensure they never instantiate more than 254 domains during their lifetime.

Generated by OpenCVE AI on October 9, 2026 at 08:51 UTC.

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History

Fri, 09 Oct 2026 19:30:00 +0000

Type Values Removed Values Added
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'total'}, 'version': '2.0.3'}


Fri, 09 Oct 2026 09:15:00 +0000

Type Values Removed Values Added
First Time appeared Zephyrproject
Zephyrproject zephyr
Vendors & Products Zephyrproject
Zephyrproject zephyr

Fri, 09 Oct 2026 07:45:00 +0000

Type Values Removed Values Added
Description The ARM64 MMU back-end allocated address space identifiers (ASIDs) for memory domains with a bare round-robin counter in arch_mem_domain_init() (arch/arm64/core/mmu.c). VM_ASID_BITS is 8, so only 255 ASIDs exist; once the counter wrapped, arch_mem_domain_init() could hand an ASID to a new domain while a still-live domain held the same one. Domain-private mappings are installed non-global (MT_NG), so the ASID is the only tag separating one domain's cached translations from another's in the TLB. The context-switch path in z_arm64_swap_ptables() only flushes the TLB when the outgoing and incoming domains carry the same ASID, which does not cover a duplicate reached through a third domain: for domains A and C sharing an ASID and an unrelated domain B, the schedule A -> B -> C never takes the flush branch, so the ASID-tagged entries A populated remain resident while C runs. Under SMP two live domains sharing an ASID can additionally be resident on two CPUs at once, which the architecture does not allow for distinct translation-table sets. Triggering the wrap requires a CONFIG_USERSPACE application on ARM64 that creates more than 255 memory domains over its lifetime; k_mem_domain_init() and k_mem_domain_deinit() are supervisor-only APIs and are not exposed as syscalls, so an unprivileged thread cannot drive the counter directly. Once two live domains alias, however, a user-mode thread in one domain can read and write memory belonging to the other domain's partitions and thread stacks with that domain's permissions, defeating the memory-domain isolation boundary. The fix scans the live domain_list before assigning an ASID, advances the round-robin counter past ASIDs already in use, and returns -ENOMEM when all are taken, so domain creation fails closed instead of silently aliasing.
Title ARM64 MMU can assign an in-use ASID to a new memory domain, breaking user-mode memory isolation
Weaknesses CWE-284
References
Metrics cvssV3_1

{'score': 7, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:H/A:H'}


Subscriptions

Zephyrproject Zephyr
cve-icon MITRE

Status: PUBLISHED

Assigner: zephyr

Published:

Updated: 2026-10-09T17:56:48.909Z

Reserved: 2026-08-11T19:47:42.367Z

Link: CVE-2026-19574

cve-icon Vulnrichment

Updated: 2026-10-09T17:56:26.208Z

cve-icon NVD

Status : Awaiting Analysis

Published: 2026-10-09T08:16:54.940

Modified: 2026-10-09T18:17:08.147

Link: CVE-2026-19574

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

Updated: 2026-10-09T09:00:03Z

Weaknesses