Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
No analysis available yet.
Remediation
No remediation available yet.
Tracking
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Advisories
| Source | ID | Title |
|---|---|---|
EUVD |
EUVD-2020-2072 | Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access. |
References
History
No history.
Status: PUBLISHED
Assigner: intel
Published:
Updated: 2024-08-04T06:02:52.194Z
Reserved: 2019-10-28T00:00:00.000Z
Link: CVE-2020-0574
No data.
Status : Modified
Published: 2020-03-12T21:15:14.373
Modified: 2024-11-21T04:53:47.337
Link: CVE-2020-0574
No data.
OpenCVE Enrichment
No data.
Weaknesses
EUVD