Description
The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
No analysis available yet.
Remediation
No remediation available yet.
Tracking
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Advisories
| Source | ID | Title |
|---|---|---|
EUVD |
EUVD-2021-6571 | The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service. |
References
History
No history.
Status: PUBLISHED
Assigner: nvidia
Published:
Updated: 2024-08-03T15:55:18.614Z
Reserved: 2020-11-12T00:00:00.000Z
Link: CVE-2021-1104
No data.
Status : Modified
Published: 2021-08-13T16:15:07.153
Modified: 2024-11-21T05:43:36.313
Link: CVE-2021-1104
No data.
OpenCVE Enrichment
No data.
Weaknesses
EUVD