Mishandling of guest SSBD selection on AMD hardware The current logic to set SSBD on AMD Family 17h and Hygon Family 18h processors requires that the setting of SSBD is coordinated at a core level, as the setting is shared between threads. Logic was introduced to keep track of how many threads require SSBD active in order to coordinate it, such logic relies on using a per-core counter of threads that have SSBD active. When running on the mentioned hardware, it's possible for a guest to under or overflow the thread counter, because each write to VIRT_SPEC_CTRL.SSBD by the guest gets propagated to the helper that does the per-core active accounting. Underflowing the counter causes the value to get saturated, and thus attempts for guests running on the same core to set SSBD won't have effect because the hypervisor assumes it's already active.
History

Fri, 22 Nov 2024 12:00:00 +0000

Type Values Removed Values Added
References

cve-icon MITRE

Status: PUBLISHED

Assigner: XEN

Published: 2023-05-17T00:00:00

Updated: 2024-08-03T13:03:45.951Z

Reserved: 2022-10-03T00:00:00

Link: CVE-2022-42336

cve-icon Vulnrichment

No data.

cve-icon NVD

Status : Modified

Published: 2023-05-17T01:15:09.480

Modified: 2024-11-21T07:24:46.820

Link: CVE-2022-42336

cve-icon Redhat

No data.