quarantine domain (dom_io) has been initialized with an address width
of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.
However dom_io being a PV domain gets the AMD-Vi IOMMU page tables
levels based on the maximum (hot pluggable) RAM address, and hence on
systems with no RAM above the 512GB mark only 3 page-table levels are
configured in the IOMMU.
On systems without RAM above the 512GB boundary
amd_iommu_quarantine_init() will setup page tables for the scratch
page with 4 levels, while the IOMMU will be configured to use 3 levels
only, resulting in the last page table directory (PDE) effectively
becoming a page table entry (PTE), and hence a device in quarantine
mode gaining write access to the page destined to be a PDE.
Due to this page table level mismatch, the sink page the device gets
read/write access to is no longer cleared between device assignment,
possibly leading to data leaks.
No advisories yet.
Solution
No solution given by the vendor.
Workaround
Not passing through physical devices to guests will avoid the vulnerability. Not using quarantine scratch-page mode will avoid the vulnerability, but could result in other issues.
Tue, 04 Nov 2025 20:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| References |
|
Tue, 17 Jun 2025 16:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Weaknesses | CWE-787 | |
| Metrics |
ssvc
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Projects
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Status: PUBLISHED
Assigner: XEN
Published:
Updated: 2025-11-04T19:25:41.611Z
Reserved: 2023-10-27T07:55:35.331Z
Link: CVE-2023-46835
Updated: 2025-11-04T19:25:41.611Z
Status : Modified
Published: 2024-01-05T17:15:11.147
Modified: 2025-11-04T20:17:10.383
Link: CVE-2023-46835
No data.
OpenCVE Enrichment
No data.