CVE-2023-46835

x86/AMD: mismatch in IOMMU quarantine page table levels

Published Jan 5, 2024 CVSS 3.1 · 5.5 Medium EPSS < 1% KEV · Not listed
Description
The current setup of the quarantine page tables assumes that the
quarantine domain (dom_io) has been initialized with an address width
of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.

However dom_io being a PV domain gets the AMD-Vi IOMMU page tables
levels based on the maximum (hot pluggable) RAM address, and hence on
systems with no RAM above the 512GB mark only 3 page-table levels are
configured in the IOMMU.

On systems without RAM above the 512GB boundary
amd_iommu_quarantine_init() will setup page tables for the scratch
page with 4 levels, while the IOMMU will be configured to use 3 levels
only, resulting in the last page table directory (PDE) effectively
becoming a page table entry (PTE), and hence a device in quarantine
mode gaining write access to the page destined to be a PDE.

Due to this page table level mismatch, the sink page the device gets
read/write access to is no longer cleared between device assignment,
possibly leading to data leaks.

Analysis

No analysis available yet

Remediation

Vendor Workaround

Not passing through physical devices to guests will avoid the vulnerability. Not using quarantine scratch-page mode will avoid the vulnerability, but could result in other issues.

Tracking

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Advisories

No advisories available
History
Type Values Removed Values Added
Weaknesses CWE-787
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Weaknesses

Sources

Status
PUBLISHED
Assigner
XEN
Published
Updated
Nov 4, 2025, 7:25 PM
Reserved
Oct 27, 2023, 7:55 AM
Status
Modified
Published
Jan 5, 2024, 5:15 PM
Modified
Jun 17, 2026, 6:31 AM