The current setup of the quarantine page tables assumes that the
quarantine domain (dom_io) has been initialized with an address width
of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.

However dom_io being a PV domain gets the AMD-Vi IOMMU page tables
levels based on the maximum (hot pluggable) RAM address, and hence on
systems with no RAM above the 512GB mark only 3 page-table levels are
configured in the IOMMU.

On systems without RAM above the 512GB boundary
amd_iommu_quarantine_init() will setup page tables for the scratch
page with 4 levels, while the IOMMU will be configured to use 3 levels
only, resulting in the last page table directory (PDE) effectively
becoming a page table entry (PTE), and hence a device in quarantine
mode gaining write access to the page destined to be a PDE.

Due to this page table level mismatch, the sink page the device gets
read/write access to is no longer cleared between device assignment,
possibly leading to data leaks.
History

Tue, 17 Jun 2025 16:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-787
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


cve-icon MITRE

Status: PUBLISHED

Assigner: XEN

Published:

Updated: 2025-06-17T16:11:08.422Z

Reserved: 2023-10-27T07:55:35.331Z

Link: CVE-2023-46835

cve-icon Vulnrichment

Updated: 2024-08-02T20:53:21.879Z

cve-icon NVD

Status : Modified

Published: 2024-01-05T17:15:11.147

Modified: 2025-06-17T16:15:23.800

Link: CVE-2023-46835

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.