The current setup of the quarantine page tables assumes that the quarantine domain (dom_io) has been initialized with an address width of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels. However dom_io being a PV domain gets the AMD-Vi IOMMU page tables levels based on the maximum (hot pluggable) RAM address, and hence on systems with no RAM above the 512GB mark only 3 page-table levels are configured in the IOMMU. On systems without RAM above the 512GB boundary amd_iommu_quarantine_init() will setup page tables for the scratch page with 4 levels, while the IOMMU will be configured to use 3 levels only, resulting in the last page table directory (PDE) effectively becoming a page table entry (PTE), and hence a device in quarantine mode gaining write access to the page destined to be a PDE. Due to this page table level mismatch, the sink page the device gets read/write access to is no longer cleared between device assignment, possibly leading to data leaks.
History

No history.

cve-icon MITRE

Status: PUBLISHED

Assigner: XEN

Published: 2024-01-05T16:34:49.531Z

Updated: 2024-09-04T19:39:59.020Z

Reserved: 2023-10-27T07:55:35.331Z

Link: CVE-2023-46835

cve-icon Vulnrichment

Updated: 2024-08-02T20:53:21.879Z

cve-icon NVD

Status : Modified

Published: 2024-01-05T17:15:11.147

Modified: 2024-11-21T08:29:23.593

Link: CVE-2023-46835

cve-icon Redhat

No data.