In the Linux kernel, the following vulnerability has been resolved:
arm64: errata: Add Cortex-A520 speculative unprivileged load workaround
Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.
The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.
The workaround isn't necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).
Metrics
Affected Vendors & Products
References
History
Mon, 04 Nov 2024 20:15:00 +0000
Type | Values Removed | Values Added |
---|---|---|
Metrics |
cvssV3_1
|
cvssV3_1
|
MITRE
Status: PUBLISHED
Assigner: Linux
Published: 2024-02-29T05:43:12.630Z
Updated: 2024-11-04T20:07:29.567Z
Reserved: 2024-02-20T12:30:33.301Z
Link: CVE-2023-52481
Vulnrichment
Updated: 2024-08-02T23:03:19.935Z
NVD
Status : Awaiting Analysis
Published: 2024-02-29T06:15:46.060
Modified: 2024-11-04T20:35:02.537
Link: CVE-2023-52481
Redhat