Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Metrics
Affected Vendors & Products
References
History
Wed, 14 Aug 2024 20:30:00 +0000
Type | Values Removed | Values Added |
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First Time appeared |
Intel
Intel processor |
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CPEs | cpe:2.3:a:intel:processor:*:*:*:*:*:*:*:* | |
Vendors & Products |
Intel
Intel processor |
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Metrics |
ssvc
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Wed, 14 Aug 2024 14:00:00 +0000
Type | Values Removed | Values Added |
---|---|---|
Description | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access. | |
Weaknesses | CWE-696 | |
References |
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Metrics |
cvssV3_1
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MITRE
Status: PUBLISHED
Assigner: intel
Published: 2024-08-14T13:45:31.607Z
Updated: 2024-08-16T04:01:35.677Z
Reserved: 2024-02-08T04:00:11.905Z
Link: CVE-2024-24853
Vulnrichment
Updated: 2024-08-14T19:17:14.428Z
NVD
Status : Awaiting Analysis
Published: 2024-08-14T14:15:21.380
Modified: 2024-08-14T17:49:14.177
Link: CVE-2024-24853
Redhat
No data.