Metrics
Affected Vendors & Products
Thu, 12 Sep 2024 10:30:00 +0000
Type | Values Removed | Values Added |
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Weaknesses | CWE-388 | |
Metrics |
cvssV3_1
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cvssV3_1
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Wed, 11 Sep 2024 13:30:00 +0000
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Metrics |
ssvc
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Mon, 19 Aug 2024 19:15:00 +0000
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References |
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Metrics |
threat_severity
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cvssV3_1
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Sat, 17 Aug 2024 09:15:00 +0000
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Description | In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. | |
Title | spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer | |
References |
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Status: PUBLISHED
Assigner: Linux
Published: 2024-08-17T09:08:46.829Z
Updated: 2024-11-05T09:39:36.669Z
Reserved: 2024-07-30T07:40:12.261Z
Link: CVE-2024-42279
Updated: 2024-09-11T12:42:23.809Z
Status : Awaiting Analysis
Published: 2024-08-17T09:15:08.880
Modified: 2024-08-19T12:59:59.177
Link: CVE-2024-42279