In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Metrics

No CVSS v4.0

Attack Vector Network

Attack Complexity Low

Privileges Required Low

Scope Unchanged

Confidentiality Impact Low

Integrity Impact Low

Availability Impact None

User Interaction None

No CVSS v3.0

No CVSS v2

This CVE is not in the KEV list.

The EPSS score is 0.00018.

Exploitation none

Automatable no

Technical Impact partial

Affected Vendors & Products

Vendors Products
Arm Subscribe
C1-premium Subscribe
C1-ultra Subscribe
Cortex-a710 Subscribe
Cortex-x2 Subscribe
Cortex-x3 Subscribe
Cortex-x4 Subscribe
Cortex-x925 Subscribe
Neoverse-v2 Subscribe
Neoverse-v3 Subscribe
Neoverse-v3ae Subscribe
Neoverse N2 Subscribe

No data.

No data.

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Vendors Products
Arm Subscribe
C1-premium Subscribe
C1-ultra Subscribe
Cortex-a710 Subscribe
Cortex-x2 Subscribe
Cortex-x3 Subscribe
Cortex-x4 Subscribe
Cortex-x925 Subscribe
Neoverse-v2 Subscribe
Neoverse-v3 Subscribe
Neoverse-v3ae Subscribe
Neoverse N2 Subscribe
Advisories

No advisories yet.

Fixes

Solution

No solution given by the vendor.

Workaround

No workaround given by the vendor.

References
Link Providers
https://developer.arm.com/documentation/111546 cve-icon cve-icon
History

Thu, 15 Jan 2026 21:15:00 +0000

Type Values Removed Values Added
Metrics cvssV3_1

{'score': 5.4, 'vector': 'CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:L/I:L/A:N'}

ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}

Thu, 15 Jan 2026 08:15:00 +0000

Type Values Removed Values Added
First Time appeared Arm
Arm c1-premium
Arm c1-ultra
Arm cortex-a710
Arm cortex-x2
Arm cortex-x3
Arm cortex-x4
Arm cortex-x925
Arm neoverse-v2
Arm neoverse-v3
Arm neoverse-v3ae
Arm neoverse N2
Vendors & Products Arm
Arm c1-premium
Arm c1-ultra
Arm cortex-a710
Arm cortex-x2
Arm cortex-x3
Arm cortex-x4
Arm cortex-x925
Arm neoverse-v2
Arm neoverse-v3
Arm neoverse-v3ae
Arm neoverse N2

Wed, 14 Jan 2026 11:15:00 +0000

Type Values Removed Values Added
Description In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Weaknesses CWE-226
References

Projects

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cve-icon MITRE

Status: PUBLISHED

Assigner: Arm

Published:

Updated: 2026-01-15T20:46:07.810Z

Reserved: 2025-01-22T14:26:41.767Z

Link: CVE-2025-0647

cve-icon Vulnrichment

Updated: 2026-01-15T20:45:54.849Z

cve-icon NVD

Status : Awaiting Analysis

Published: 2026-01-14T11:15:50.027

Modified: 2026-01-15T21:16:02.100

Link: CVE-2025-0647

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

Updated: 2026-01-15T08:03:33Z

Weaknesses