Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
No analysis available yet.
Remediation
No remediation available yet.
Tracking
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Advisories
| Source | ID | Title |
|---|---|---|
EUVD |
EUVD-2025-19672 | Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks. |
References
History
Wed, 02 Jul 2025 14:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Weaknesses | CWE-266 | |
| Metrics |
cvssV3_1
|
Tue, 01 Jul 2025 20:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks. | |
| References |
|
Subscriptions
No data.
Status: PUBLISHED
Assigner: mitre
Published:
Updated: 2025-07-02T13:58:38.672Z
Reserved: 2025-04-22T00:00:00.000Z
Link: CVE-2025-45006
Updated: 2025-07-02T13:55:40.154Z
Status : Awaiting Analysis
Published: 2025-07-01T20:15:24.993
Modified: 2025-07-03T15:14:12.767
Link: CVE-2025-45006
No data.
OpenCVE Enrichment
No data.
Weaknesses
EUVD