Description
The ITE IT8xxx2 SHI host-command backend (subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_ite.c) copied the 8-byte host-command request header from the SPI Rx FIFO directly into the shared receive buffer data->in_msg and only afterwards checked the protocol version and the derived packet length. The interrupt handler also accepted a chip-select assertion and an Rx-valid-length (RVLI) interrupt in any driver state other than SHI_STATE_DISABLED, so a new header could be parsed while the host-command thread was still processing the previous request out of the very same buffer.

The host processor is the SPI controller and drives both chip select and the clock. After sending a well-formed request it can immediately de-assert chip select — which returns the driver to the ready state and re-enables the FIFO — and start a second transaction carrying a header with data_len = 0xFFFF. Those eight bytes are written into in_msg before the oversized length is rejected, so they land in a buffer whose contents verify_rx() in subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c has already validated. If this lands in the window before the host-command thread executes args.input_buf_size = rx_header->data_len, the framework hands the registered command handler a 65535-byte input length over a 256-byte buffer.

The result is an out-of-bounds read of up to roughly 64 KiB beyond the request buffer: command handlers that copy or echo input_buf_size bytes disclose adjacent embedded-controller memory back to the host or overflow the response buffer, and a read past the end of SRAM faults the controller. The same race also allows cmd_id and cmd_ver to be swapped after checksum verification and after handler lookup. Exploitation requires the ability to drive the inter-processor SHI bus (a compromised host OS or physical access to the SPI lines) and winning a timing race, which the SPI controller can retry indefinitely.

The fix parses the header into a local struct ec_host_cmd_request_header and copies it into in_msg only after the length has been bounded by sizeof(data->in_msg), and ignores chip-select and RVLI interrupts outside SHI_STATE_READY_TO_RECV/SHI_STATE_RECEIVING. A residual, bounded race remains: an end-of-transaction interrupt still resets the state to ready while the host-command thread owns the buffer, so a valid second request can still overwrite the in-flight request's contents, unlike the NPCX backend which parks in SHI_STATE_CNL_RESP_NOT_RDY while the buffer is in use.
Published: 2026-10-09
Score: 6.7 Medium
EPSS: < 1% Very Low
KEV: No
Impact: Information disclosure and potential denial of service
Action: Immediate Patch
AI Analysis

Impact

The ITE IT8xxx2 SHI host-command backend contains a data race that allows a second SPI request to override the length field of a request still being processed. Because the driver copies the 8‑byte header directly into the shared in‑msg buffer before checking the protocol version or the derived packet length, an attacker can supply a header with data_len set to 0xFFFF. When the host command thread later assigns this length to input_buf_size, the command handler receives a request length that far exceeds the 256‑byte request buffer, resulting in an out‑of‑bounds read of up to roughly 64 KiB. Handlers that copy or echo this length can leak memory adjacent to the control block, while overflow of the response buffer can cause a controller fault. The flaw therefore leads to memory disclosure and a potential crash.

Affected Systems

Affected systems are Zephyr RTOS releases that include the unpatched SHI host‑command backend. No specific product version range is listed in the advisory, so any build containing the vulnerable ec_host_cmd_backend_shi_ite.c implementation is impacted. The vulnerability exists in the Zephyr project’s source tree prior to the commit that manages header parsing and interrupt handling.

Risk and Exploitability

The CVSS score of 6.7 indicates a medium‑severity flaw, and the EPSS score is not available. The vulnerability is not listed in the CISA Known Exploited Vulnerabilities catalog. Exploitation requires an attacker to control the inter‑processor SHI bus by compromising the host operating system or gaining physical access to the SPI lines and to orchestrate a timing race that repeats the transaction. Because the SPI controller can retry indefinitely, the race can be attempted repeatedly, but the attack still requires low‑level access to the hardware or a privileged host. Consequently the risk is moderate, but the potential impact of memory disclosure in a controller environment is significant.

Generated by OpenCVE AI on October 9, 2026 at 08:22 UTC.

Remediation

No solution or workaround provided in the CVE record.

OpenCVE Recommended Actions

  • Update Zephyr to a version that includes the commit 0636e65c825e810a which bounds the header parsing and ignores out‑of‑state interrupts.
  • Re‑compile the firmware after applying the patch and verify that ec_host_cmd_backend_shi_ite.c uses the new header processing logic.
  • If the SHI host‑command interface is not required, disable the SHI driver or configure the system to ignore host‑command packets from the SPI bus.

Generated by OpenCVE AI on October 9, 2026 at 08:22 UTC.

Tracking

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Advisories

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History

Fri, 09 Oct 2026 19:30:00 +0000

Type Values Removed Values Added
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


Fri, 09 Oct 2026 09:15:00 +0000

Type Values Removed Values Added
First Time appeared Zephyrproject
Zephyrproject zephyr
Vendors & Products Zephyrproject
Zephyrproject zephyr

Fri, 09 Oct 2026 07:45:00 +0000

Type Values Removed Values Added
Description The ITE IT8xxx2 SHI host-command backend (subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_ite.c) copied the 8-byte host-command request header from the SPI Rx FIFO directly into the shared receive buffer data->in_msg and only afterwards checked the protocol version and the derived packet length. The interrupt handler also accepted a chip-select assertion and an Rx-valid-length (RVLI) interrupt in any driver state other than SHI_STATE_DISABLED, so a new header could be parsed while the host-command thread was still processing the previous request out of the very same buffer. The host processor is the SPI controller and drives both chip select and the clock. After sending a well-formed request it can immediately de-assert chip select — which returns the driver to the ready state and re-enables the FIFO — and start a second transaction carrying a header with data_len = 0xFFFF. Those eight bytes are written into in_msg before the oversized length is rejected, so they land in a buffer whose contents verify_rx() in subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c has already validated. If this lands in the window before the host-command thread executes args.input_buf_size = rx_header->data_len, the framework hands the registered command handler a 65535-byte input length over a 256-byte buffer. The result is an out-of-bounds read of up to roughly 64 KiB beyond the request buffer: command handlers that copy or echo input_buf_size bytes disclose adjacent embedded-controller memory back to the host or overflow the response buffer, and a read past the end of SRAM faults the controller. The same race also allows cmd_id and cmd_ver to be swapped after checksum verification and after handler lookup. Exploitation requires the ability to drive the inter-processor SHI bus (a compromised host OS or physical access to the SPI lines) and winning a timing race, which the SPI controller can retry indefinitely. The fix parses the header into a local struct ec_host_cmd_request_header and copies it into in_msg only after the length has been bounded by sizeof(data->in_msg), and ignores chip-select and RVLI interrupts outside SHI_STATE_READY_TO_RECV/SHI_STATE_RECEIVING. A residual, bounded race remains: an end-of-transaction interrupt still resets the state to ready while the host-command thread owns the buffer, so a valid second request can still overwrite the in-flight request's contents, unlike the NPCX backend which parks in SHI_STATE_CNL_RESP_NOT_RDY while the buffer is in use.
Title Race condition in ITE IT8xxx2 SHI host-command backend lets a second SPI request write an unvalidated length into the in-flight request buffer
Weaknesses CWE-362
References
Metrics cvssV3_1

{'score': 6.7, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:U/C:H/I:N/A:H'}


Subscriptions

Zephyrproject Zephyr
cve-icon MITRE

Status: PUBLISHED

Assigner: zephyr

Published:

Updated: 2026-10-09T17:57:42.905Z

Reserved: 2026-08-11T19:15:07.946Z

Link: CVE-2026-19571

cve-icon Vulnrichment

Updated: 2026-10-09T17:57:32.543Z

cve-icon NVD

Status : Awaiting Analysis

Published: 2026-10-09T08:16:54.817

Modified: 2026-10-09T18:17:08.020

Link: CVE-2026-19571

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

Updated: 2026-10-09T09:00:03Z

Weaknesses
  • CWE-362

    Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')