A local attacker who can execute privileged CSR operations on a XiangShan processor may carefully read and write the menvcfg register to set reserved bits in the machine status view. This manipulation violates the RISC‑V WPRI rule, which requires software to leave reserved bits unchanged. The resulting corruption of the status register can alter privilege levels, bypass security checks, or destabilise the processor, potentially leading to privilege escalation or denial of service. The vulnerability is therefore an internal flaw that requires local, privileged code execution.

XiangShan firmware (OpenXiangShan) versions based on commit aecf601e803bfd2371667a3fb60bfcd83c333027 released 2024‑11‑19 are affected. No other vendors or products are listed as impacted.

Because the exploit requires privileged CSR access, it is a local attack that normally implies root or firmware‑level control. No EPSS score or KEV listing is available, and a CVSS score is not provided, so the exact severity cannot be quantified. However, the ability to corrupt reserved status bits suggests a high risk for the affected system: an adversary with the necessary privileges could gain additional privileges, disrupt correct operation, or cause a system crash. The attack path is straightforward: obtain privileged CSR access, read or write menvcfg, and set the reserved bits in xstatus, thereby violating the intended hardware semantics.