A race condition exists when the TLBI;DSB sequence used to invalidate TLB entries may complete before the global observation of memory writes that were performed via an invalidated TLB entry. The errata does not affect the actual invalidation of the TLB entries; the problem only concerns the order in which memory writes become visible system‑wide, potentially leaving kernel memory in an inconsistent state after a write operation. This flaw is limited to memory accesses that have been translated by an affected invalidated TLB entry.

All Linux kernels for arm64 CPUs that exhibit the listed TLBI errata, as identified in the errata tables referenced in the advisory. The workaround is applied by enabling CONFIG_ARM64_WORKAROUND_REPEAT_TLBI in the kernel configuration for each affected CPU family.

The CVSS score of 8.8 indicates a high impact, while the EPSS score of less than 1% indicates a very low likelihood of exploitation in the wild. The vulnerability is not listed in the CISA KEV catalog, and no public exploits are available. The vulnerability requires kernel execution privileges or an attacker’s ability to trigger the race condition; based on the description, it is inferred that an attacker with sufficient privilege would need to orchestrate a timing window between memory writes and the TLBI;DSB sequence to exploit the flaw, which is impractical under normal operation.