Description
In the Linux kernel, the following vulnerability has been resolved:

spi: spi-qpic-snand: write the feature value before executing SET_FEATURE

qcom_spi_send_cmdaddr() programs NAND_FLASH_CMD/NAND_EXEC_CMD and submits
the descriptors, which makes the controller execute the command
immediately. For SPINAND_SET_FEATURE the value to be written is only
placed into NAND_FLASH_FEATURES afterwards, by qcom_spi_io_op(), in a
second submission - so the chip is programmed with whatever that register
happened to hold from a previous operation, and the intended value is only
applied by the *next* SET_FEATURE.

Measured on a TP-Link Archer AX55 v1 (IPQ5018, ESMT F50L1G41LB): writing
0x40 to the configuration register (0xb0) leaves the chip at 0x00, and the
subsequent write of 0x00 leaves it at 0x40 - every write lands one
operation late.

This stayed unnoticed until v6.18 added SPI-NAND OTP support together
with OTP entries for ESMT chips. spinand_otp_rw() enables OTP mode,
reads, and disables it again, and mtd_otp_nvmem_add() does this during
MTD registration. With the off-by-one, the "disable" write actually
applies the previously requested value, so CFG_OTP_ENABLE ends up set:
the chip stays in OTP mode, every subsequent array read returns the OTP
area instead of the array (UBI reports an empty device) and all writes
fail with -EIO because the OTP area is write protected. On this board
that makes the whole flash unusable and the device unbootable.

Write the feature value into NAND_FLASH_FEATURES as part of the same
transaction, before NAND_EXEC_CMD. While at it, copy only the bytes the
operation actually carries - the previous code dereferenced a 4-byte
pointer on a one-byte buffer (spinand->scratchbuf).

With this patch the flash contents read back bit-identical to a
known-good dump of the same board taken under the vendor firmware
(md5-verified across partitions), and writes work.
Published: 2026-08-28
Score: 8.4 High
EPSS: < 1% Very Low
KEV: No
Impact: Device Unavailability (flash corruption and boot failure)
Action: Apply Fix
AI Analysis

Impact

The kernel fault causes the value written to a NAND feature register to be applied one command late, because the SET_FEATURE operation writes the feature value after the command is already executed. On systems that use SPI‑NAND OTP support, this off‑by‑one error means that a configuration write intended to disable OTP mode actually applies the previous value, leaving the chip permanently in OTP mode. Subsequent array reads therefore return the OTP area and all writes fail, rendering the flash unusable and preventing the system from booting. Additionally, the code dereferences a pointer larger than the intended buffer when copying data into the scratch buffer, which could lead to memory corruption and instability if an attacker can influence the contents. The impact is primarily data integrity and availability loss; no evidence of remote code execution is present in the disclosed behavior.

Affected Systems

Linux kernel releases that include the SPI‑NAND driver for QPIC SPINAND chips, particularly versions that added OTP support such as 6.18 and later. Devices that implement the OTP feature, like the TP‑Link Archer AX55 v1 (IPQ5018 SoC with ESMT NAND), have demonstrably experienced flash corruption and boot failure.

Risk and Exploitability

The EPSS score is below 1% and the vulnerability is not listed in CISA KEV. The CVSS score is 8.4, indicating high severity. The flaw occurs in low-level flash handling code and requires local code execution or the ability to trigger SPI‑NAND writes. The attack vector is not explicitly documented, but the described scenario implies that a local attacker capable of influencing kernel flash operations could exploit the bug. The severity is high because the flaw directly destroys the boot media, and the exploit would render the device unusable.

Generated by OpenCVE AI on August 31, 2026 at 13:52 UTC.

Remediation

No vendor fix or workaround currently provided.

OpenCVE Recommended Actions

  • Update the Linux kernel to a release that contains the corrected spinand driver (e.g., 6.19 or later).
  • Reboot the device so the driver reloads with the proper initialization.
  • Until the kernel update is applied, refrain from modifying the CONFIGURATION register or enabling OTP mode to avoid persisting in OTP.

Generated by OpenCVE AI on August 31, 2026 at 13:52 UTC.

Tracking

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Advisories

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History

Mon, 31 Aug 2026 12:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-805
References
Metrics threat_severity

None

threat_severity

Moderate


Sat, 29 Aug 2026 09:00:00 +0000

Type Values Removed Values Added
Weaknesses CWE-119
CWE-120

Sat, 29 Aug 2026 06:45:00 +0000

Type Values Removed Values Added
Metrics cvssV3_1

{'score': 8.4, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H'}


Fri, 28 Aug 2026 17:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-119
CWE-120

Fri, 28 Aug 2026 13:15:00 +0000

Type Values Removed Values Added
Weaknesses CWE-119
CWE-125
CWE-482

Fri, 28 Aug 2026 11:45:00 +0000

Type Values Removed Values Added
Weaknesses CWE-119
CWE-125
CWE-482

Fri, 28 Aug 2026 07:30:00 +0000

Type Values Removed Values Added
Description In the Linux kernel, the following vulnerability has been resolved: spi: spi-qpic-snand: write the feature value before executing SET_FEATURE qcom_spi_send_cmdaddr() programs NAND_FLASH_CMD/NAND_EXEC_CMD and submits the descriptors, which makes the controller execute the command immediately. For SPINAND_SET_FEATURE the value to be written is only placed into NAND_FLASH_FEATURES afterwards, by qcom_spi_io_op(), in a second submission - so the chip is programmed with whatever that register happened to hold from a previous operation, and the intended value is only applied by the *next* SET_FEATURE. Measured on a TP-Link Archer AX55 v1 (IPQ5018, ESMT F50L1G41LB): writing 0x40 to the configuration register (0xb0) leaves the chip at 0x00, and the subsequent write of 0x00 leaves it at 0x40 - every write lands one operation late. This stayed unnoticed until v6.18 added SPI-NAND OTP support together with OTP entries for ESMT chips. spinand_otp_rw() enables OTP mode, reads, and disables it again, and mtd_otp_nvmem_add() does this during MTD registration. With the off-by-one, the "disable" write actually applies the previously requested value, so CFG_OTP_ENABLE ends up set: the chip stays in OTP mode, every subsequent array read returns the OTP area instead of the array (UBI reports an empty device) and all writes fail with -EIO because the OTP area is write protected. On this board that makes the whole flash unusable and the device unbootable. Write the feature value into NAND_FLASH_FEATURES as part of the same transaction, before NAND_EXEC_CMD. While at it, copy only the bytes the operation actually carries - the previous code dereferenced a 4-byte pointer on a one-byte buffer (spinand->scratchbuf). With this patch the flash contents read back bit-identical to a known-good dump of the same board taken under the vendor firmware (md5-verified across partitions), and writes work.
Title spi: spi-qpic-snand: write the feature value before executing SET_FEATURE
First Time appeared Linux
Linux linux Kernel
CPEs cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*
Vendors & Products Linux
Linux linux Kernel
References

Subscriptions

Linux Linux Kernel
cve-icon MITRE

Status: PUBLISHED

Assigner: Linux

Published:

Updated: 2026-08-29T06:22:28.248Z

Reserved: 2026-08-26T14:34:25.788Z

Link: CVE-2026-80712

cve-icon Vulnrichment

No data.

cve-icon NVD

Status : Received

Published: 2026-08-28T08:16:56.850

Modified: 2026-08-29T07:16:52.640

Link: CVE-2026-80712

cve-icon Redhat

Severity : Moderate

Publid Date: 2026-08-28T00:00:00Z

Links: CVE-2026-80712 - Bugzilla

cve-icon OpenCVE Enrichment

Updated: 2026-08-31T14:00:19Z

Weaknesses
  • CWE-805

    Buffer Access with Incorrect Length Value