An implementation flaw in several Arm CPU families allows code executing at a lower exception level to write directly to memory regions or resources that are protected at a higher exception level. The race‑condition type vulnerability is inferred from the description and enables an attacker to overwrite privileged registers, configuration data, or secure memory, potentially injecting malicious code or altering system state. The result is a full privilege escalation that jeopardises the confidentiality, integrity, and availability of the entire system.

Vendors and processors impacted include Arm C1‑Ultra and C1‑Premium embedded cores, all Arm Neoverse V1, V2, V3, and V3AE server and data‑center variants, Neoverse‑N1 and Neoverse‑N2, and the Cortex‑X family from X1 and X1C up through X925, and the Cortex‑A family variants A710, A78, A78AE, A78C, A77, A76, and A76AE.

The flaw relies on a race condition between privilege levels, inferred from the description; exploitation requires the attacker to be able to run code at a lower exception level and time writes precisely to the protected resource. The EPSS score is less than 1% and the vulnerability is not listed in CISA’s KEV catalog, indicating a modest exploitation probability. The CVSS score of 9.1 confirms the high severity and that a successful compromise would grant complete control over the device, making this vulnerability a high risk from a security standpoint when vulnerable code is present.