Description
The Microchip SERCOM-G1 UART driver (drivers/serial/uart_mchp_sercom_g1.c), used by the PIC32CM-JH SoC family, contains an out-of-bounds write in its asynchronous (DMA) receive path. When uart_rx_enable() is invoked with a one-byte receive buffer (len == 1) and CONFIG_UART_MCHP_ASYNC is enabled, the RX-complete ISR starts a single-beat DMA transfer while a received byte is already pending in the SERCOM DATA register. On this SoC the peripheral-triggered DMA start sequencing then writes one byte past the end of the caller-supplied buffer (CWE-787). The overflowed byte's value is the UART RX data supplied by the connected serial peer (adjacent attacker), while its size and location are fixed at one byte immediately after the buffer. Exploitation requires the async UART config (not enabled by default on the in-tree PIC32CM-JH boards) and a consumer that enables RX with a one-byte buffer; impact is limited single-byte memory corruption adjacent to the RX buffer (possible crash / denial of service). The defect shipped in v4.4.0. The fix reads the first byte with the CPU and, for one-byte buffers, performs no DMA at all; for larger buffers it sizes the DMA for the remaining len-1 bytes.
Published: 2026-06-28
Score: 4.2 Medium
EPSS: n/a
KEV: No
Impact: n/a
Action: n/a
AI Analysis

Impact

An out-of-bounds write occurs in the Microchip SERCOM-G1 UART driver when asynchronous DMA receive is enabled and a caller requests a one‑byte receive buffer. The DMA engine writes one byte past the end of the supplied buffer, exposing the adjacent memory to overwrite with received UART data. This flaw can induce a single‑byte memory corruption that may lead to a crash or denial of service, but it does not provide direct code execution or broader system compromise.

Affected Systems

The vulnerability affects the Zephyr kernel when it includes the Microchip SERCOM-G1 UART driver for the PIC32CM‑JH family of SoCs. The defect was present in kernel version 4.4.0 and earlier; any release that has not incorporated the specific commit that disables DMA for one‑byte buffers remains vulnerable.

Risk and Exploitability

The CVSS score of 4.2 indicates a medium impact severity. EPSS is not available, and the issue is not recorded in CISA’s KEV catalog, suggesting limited public exploitation. The exploit requires that asynchronous UART is configured (CONFIG_UART_MCHP_ASYNC enabled) and that a user explicitly enables a one‑byte receive buffer; these prerequisites are not enabled by default on the in‑tree PIC32CM‑JH boards. While the attack surface is narrow, an adjacent attacker connected to the UART could trigger the overflow and cause a crash if the conditions are met.

Generated by OpenCVE AI on June 28, 2026 at 06:21 UTC.

Remediation

No vendor fix or workaround currently provided.

OpenCVE Recommended Actions

  • Update the Zephyr source tree to a version that includes the commit 5251d2bc0070be801769fb7ce7b9066fef5d9f81, which fixes the DMA handling for one‑byte buffers
  • If asynchronous UART must be used, avoid configuring a one‑byte receive buffer; use a larger buffer or synchronous mode instead
  • Disable CONFIG_UART_MCHP_ASYNC in projects that do not require asynchronous DMA reception

Generated by OpenCVE AI on June 28, 2026 at 06:21 UTC.

Tracking

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Advisories

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History

Sun, 28 Jun 2026 05:00:00 +0000

Type Values Removed Values Added
Description The Microchip SERCOM-G1 UART driver (drivers/serial/uart_mchp_sercom_g1.c), used by the PIC32CM-JH SoC family, contains an out-of-bounds write in its asynchronous (DMA) receive path. When uart_rx_enable() is invoked with a one-byte receive buffer (len == 1) and CONFIG_UART_MCHP_ASYNC is enabled, the RX-complete ISR starts a single-beat DMA transfer while a received byte is already pending in the SERCOM DATA register. On this SoC the peripheral-triggered DMA start sequencing then writes one byte past the end of the caller-supplied buffer (CWE-787). The overflowed byte's value is the UART RX data supplied by the connected serial peer (adjacent attacker), while its size and location are fixed at one byte immediately after the buffer. Exploitation requires the async UART config (not enabled by default on the in-tree PIC32CM-JH boards) and a consumer that enables RX with a one-byte buffer; impact is limited single-byte memory corruption adjacent to the RX buffer (possible crash / denial of service). The defect shipped in v4.4.0. The fix reads the first byte with the CPU and, for one-byte buffers, performs no DMA at all; for larger buffers it sizes the DMA for the remaining len-1 bytes.
Title Out-of-bounds write in Microchip SERCOM-G1 (PIC32CM-JH) async UART RX with 1-byte buffer
Weaknesses CWE-787
References
Metrics cvssV3_1

{'score': 4.2, 'vector': 'CVSS:3.1/AV:A/AC:H/PR:N/UI:N/S:U/C:N/I:L/A:L'}


Subscriptions

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cve-icon MITRE

Status: PUBLISHED

Assigner: zephyr

Published:

Updated: 2026-06-28T04:02:47.441Z

Reserved: 2026-06-02T15:11:46.303Z

Link: CVE-2026-10644

cve-icon Vulnrichment

No data.

cve-icon NVD

No data.

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

Updated: 2026-06-28T06:30:04Z

Weaknesses